SRL
Like SRA, except a 0 is put into bit 7. The bits are all shifted right, with bit 0 put into the carry flag.
Syntax
SRL A
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L
SRL (HL)
SRL (IX+d)
SRL (IY+d)
Allowed Instructions
Effects
S, H, and N flags reset, Z if result is zero, P/V set if parity is even, C from bit 0.
Uses
T-States
r denotes 8-bit register.
| r | 8 |
| (hl) | 15 |
| (ix+X) | 23 |
| (iy+X) | 23 |
See Also
page revision: 2, last edited: 16 Dec 2014 18:48
