Sum of second operand and carry flag is subtracted from the first operand. Results are written into the first operand.


sbc a,op8    ;8 bits
sbc hl,op16    ;16 bits

Allowed Instructions

sbc a,a
sbc a,b
sbc a,c
sbc a,d
sbc a,e
sbc a,h
sbc a,l
sbc a,ixh
sbc a,ixl
sbc a,iyh
sbc a,iyl
sbc a,(hl)
sbc a,(ix+n)
sbc a,(iy+n)
sbc a,n        ;8 bits

sbc hl,bc
sbc hl,de
sbc hl,hl
sbc hl,sp


N flag is set, P/V detects overflow, rest modified by definition.

In the case of 16-bit registers, h flag is undefined.


Multiple precision subtraction


r denotes 8-bit register.
rr represents a two byte register pair: BC, DE, HL, SP

r 4
X 7
(hl) 7
(ix+X) 19
(iy+X) 19
hl, rr 15

See Also


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